Silicide Engineering to Boost Si Tunnel Transistor Drive Current

Abstract

In this paper, we present for the first time a novel Si p-tunnel field effect transistor (pTFET) with high-k dielectric and metal gate fabricated in a multiple gate technology. The device exhibits an on-state current of 7 µA/µm at V _DD of 0.9 V and a high I _ON/I _OFF ratio of ∼10⁶ with a fin width of 10 nm. The high on-current is believed to be due to an enhanced electric field caused by silicide encroachment and dopant segregation. Low variability of the device performance is reported for the different fin widths. Temperature measurements also show that the current is due to different transport mechanisms at different gate biases. Temperature measurements and TCAD simulations both confirm the presence of trap-assisted tunneling (TAT) as main responsible for the degradation of the subthreshold swing.