Numerical simulation of vertical tunnelling field-effect transistors charge-trapping memory with TCAD tools

Abstract

A novel vertical tunnelling field-effect transistor (TFET) based on silicon-oxide-nitride-oxide-silicon (SONOS) non-volatile memory device, named as VT-SONOS, is proposed and investigated using TCAD simulations. Different from traditional planar TFET-based SONOS memory, the VT-SONOS device is programmed via band-to-band tunnelling for vertical pocket and Fowler–Nordheim tunnelling for both pocket/bottom oxide (OX_b) and channel/OX_b regions, which leads to a steeper subthreshold swing (SS) and a larger on-state current (I _ON). The device structure is constructed using Sentaurus TCAD tools, and I _D–V _G characteristics were extracted using TCAD tools. Obtained SS value is 102.09 mV dec⁻¹, while the I _ON was 3.02 × 10⁻⁴ A. The memory window was 2.95 V, showing more dependence on programming pulse height (V _gp) than erasing pulse height (V _ge). Furthermore, 10-year retention characteristics were studied to investigate critical reliability issue. About 60% of the initial trapped charges remained in the device after unbiased 3.15 × 10⁸ s (10 years) storage.