CMOS scaling beyond 32nm
- 26 July 2009
- conference paper
- conference paper
- Published by Association for Computing Machinery (ACM)
- p. 310-313
- https://doi.org/10.1145/1629911.1629996
Abstract
This paper explores the challenges and opportunities facing CMOS process generations past the 32nm technology node. Planar and multiple-gate devices are compared and contrasted. Resistance and capacitance challenges are reviewed in relation to past history and on-going research. Key enhancers such as high-k metal-gate (HiK-MG), substrate and channel orientation, and NMOS and PMOS strain, are discussed in relation to the challenges of the coming transistor generations.Keywords
This publication has 7 references indexed in Scilit:
- Spacer Removal Technique for Boosting Strain in n-Channel FinFETs With Silicon-Carbon Source and Drain StressorsIEEE Electron Device Letters, 2007
- Schottky-Barrier Height Tuning by Means of Ion Implantation Into Preformed Silicide Films Followed by Drive-In AnnealIEEE Electron Device Letters, 2007
- AgendaRevue Française d'Allergologie et d'Immunologie Clinique, 2007
- CMOS Circuit Performance Enhancement by Surface Orientation OptimizationIEEE Transactions on Electron Devices, 2004
- High-$kappa$/Metal–Gate Stack and Its MOSFET CharacteristicsIEEE Electron Device Letters, 2004
- Thickness limitations of SiO/sub 2/ gate dielectrics for MOS ULSIIEEE Transactions on Electron Devices, 1990
- Design of ion-implanted MOSFET's with very small physical dimensionsIEEE Journal of Solid-State Circuits, 1974