Statistical Characterization of Noise and Interference in NAND Flash Memory
- 11 February 2013
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Circuits and Systems I: Regular Papers
- Vol. 60 (8), 2153-2164
- https://doi.org/10.1109/tcsi.2013.2239116
Abstract
Given the limited set of empirical input/output data from flash memory cells, we describe a technique to statistically analyze different sources that cause the mean-shifts and random fluctuations in the read values of the cells. In particular, for a given victim cell, we are able to quantify the amount of interference coming from any arbitrarily chosen set of potentially influencing cells. The effect of noise and interference on the victim cell after repeated program/erase cycles as well as baking is also investigated. The results presented here can be used to construct a channel model with data-dependent noise and interference characteristics, which in turn can be utilized in designing and evaluating advanced coding and signal processing methods for flash memory.Keywords
This publication has 10 references indexed in Scilit:
- Noise and interference characterization for MLC flash memoriesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2012
- A MPCN-Based Parallel Architecture in BCH Decoders for nand Flash Memory DevicesIEEE Transactions on Circuits and Systems II: Express Briefs, 2011
- On the Use of Soft-Decision Error-Correction Codes in nand Flash MemoryIEEE Transactions on Circuits and Systems I: Regular Papers, 2010
- Using Data Postcompensation and Predistortion to Tolerate Cell-to-Cell Interference in MLC nand Flash MemoryIEEE Transactions on Circuits and Systems I: Regular Papers, 2010
- Data retention characteristics of sub-100 nm NAND flash memory cellsIEEE Electron Device Letters, 2003
- A new technique for measuring threshold voltage distribution in flash EEPROM devicesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Effects of floating-gate interference on NAND flash memory cell operationIEEE Electron Device Letters, 2002
- A 3.3 V 32 Mb NAND flash memory with incremental step pulse programming schemeIEEE Journal of Solid-State Circuits, 1995
- Optimal decoding of linear codes for minimizing symbol error rate (Corresp.)IEEE Transactions on Information Theory, 1974
- The viterbi algorithmProceedings of the IEEE, 1973