A MPCN-Based Parallel Architecture in BCH Decoders for nand Flash Memory Devices
- 8 September 2011
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Circuits and Systems II: Express Briefs
- Vol. 58 (10), 682-686
- https://doi.org/10.1109/TCSII.2011.2161704
Abstract
According to large-page-size and random-bit-error characteristics, long-block-length Bose-Chaudhuri-Hochquenghem (BCH) decoders are applied to realize error correction in NAND Flash memory devices. To accelerate the decoding process in an area-efficient architecture, a parallel architecture with minimal polynomial combinational network (MPCN) for long BCH decoders is presented in this brief. The proposed design utilizes MPCNs to replace constant finite-field multipliers, which dominate the hardware complexity of the high-parallel Chien search architecture. Furthermore, both the syndrome calculator and the Chien search can be merged by exploiting our MPCN-based architecture, leading to significant hardware complexity reduction. From the synthesis results in the 90-nm CMOS technology, the MPCN-based joint syndrome calculation and Chien search has 46.7% gate count saving for parallel-32 BCH (4603, 4096; 39) decoder in contrast with the straightforward design.Keywords
This publication has 7 references indexed in Scilit:
- Improving Multi-Level NAND Flash Memory Storage Reliability Using Concatenated BCH-TCM CodingIEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2009
- VLSI Implementation of BCH Error Correction for Multilevel Cell NAND Flash MemoryIEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2009
- Strength-Reduced Parallel Chien Search Architecture for Strong BCH CodesIEEE Transactions on Circuits and Systems II: Express Briefs, 2008
- A 70 nm 16 Gb 16-Level-Cell NAND flash MemoryIEEE Journal of Solid-State Circuits, 2008
- Small area parallel Chien search architectures for long BCH codesIEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2004
- A low-power Reed-Solomon decoder for STM-16 optical communicationsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- 10- and 40-Gb/s forward error correction devices for optical communicationsIEEE Journal of Solid-State Circuits, 2002