A 3.3 V 32 Mb NAND flash memory with incremental step pulse programming scheme
- 1 January 1995
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 30 (11), 1149-1156
- https://doi.org/10.1109/4.475701
Abstract
No abstract availableThis publication has 5 references indexed in Scilit:
- High-Speed Programming and Program-Verify Methods Suitable for Low-Voltage Flash MemoriesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- An experimental 4 Mb CMOS EEPROM with a NAND structured cellPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A quick intelligent program architecture for 3 V-only NAND-EEPROMsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A 2.3 mu m/sup 2/ memory cell structure for 16 Mb NAND EEPROMsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A 34 Mb 3.3 V serial flash EEPROM for solid-state disk applicationsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002