Quantitative evaluation of process-induced line-edge roughness in FinFET: Bayesian regression model

Abstract

With the aggressive scaling down of the minimum feature size of advanced metal–oxide–semiconductor (MOS) devices, it has become imperative to design and fabricate process-variation-immune devices. Technology computer-aided design (TCAD) simulations are typically used to test thousands of devices for process-variation immunity, but the process is computationally expensive. In this work, we propose a novel approach to simulate and predict the current–voltage characteristics of fin field-effect transistor devices with process-induced line-edge roughness (LER), within a few seconds. We exploit the Bayesian linear regression (BLR) model to estimate the mean and standard deviation of the drain-to-source current (IDS) for an arbitrary gate voltage (VGS) and LER profile. We evaluate the prediction accuracy in terms of the mean absolute percentage error (MAPE) and root-mean-squared error (RMSE). The MAPEs for the mean and standard deviation of IDS are < 1 % and < 20 %, respectively, and the corresponding RMSEs are 0.0804 and 0.0263, respectively. Once the IDS–VGS distribution is estimated by means of this novel approach, the distributions of other device metrics such as the threshold voltage and off-state leakage current can be estimated.