Intrinsic parameter fluctuations in decananometer mosfets introduced by gate line edge roughness
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- 15 July 2003
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 50 (5), 1254-1260
- https://doi.org/10.1109/ted.2003.813457
Abstract
In this paper, we use statistical three-dimensional (3-D) simulations to study the impact of the gate line edge roughness (LER) on the intrinsic parameters fluctuations in deep decananometer (sub 50 nm) gate MOSFETs. The line edge roughness is introduced using a Fourier synthesis technique based on the power spectrum of a Gaussian autocorrelation function. In carefully designed simulation experiments, we investigate the impact of the rms amplitude /spl Delta/ and the correlation length /spl Lambda/ on the intrinsic parameter fluctuations in well scaled, but simple devices with fixed geometry as well as the channel length and width dependence of the fluctuations at fixed LER parameters. For the first time, we superimpose in the simulations LER and random discrete dopants and investigate their relative contribution to the intrinsic parameter fluctuations in the investigated devices. For particular MOSFET geometries, we were able to identify the regions where each of these two sources of intrinsic parameter fluctuations dominates.Keywords
This publication has 18 references indexed in Scilit:
- The effects of development parameter on line edge roughness in sub-0.20 μm line patternsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and ni SALICIDEPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Modeling line edge roughness effects in sub 100 nanometer gate length devicesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Metrology method for the correlation of line edge roughness for different resists before and after etchMicroelectronic Engineering, 2001
- An experimentally validated analytical model for gate line-edge roughness (LER) effects on technology scalingIEEE Electron Device Letters, 2001
- Analysis of Statistical Fluctuations due to Line Edge Roughness in sub-0.1μm MOSFETsPublished by Springer Science and Business Media LLC ,2001
- Resolution limiting mechanism in electron beam lithographyElectronics Letters, 2000
- Demonstration of pattern transfer into sub-100 nm polysilicon line/space features patterned with extreme ultraviolet lithographyJournal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures, 1999
- Reduction of line edge roughness in the top surface imaging processJournal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures, 1998
- High resolution studies on Hoechst AZ PN114 chemically amplified resistMicroelectronic Engineering, 1996