3-D Quasi-Atomistic Model for Line Edge Roughness in Nonplanar MOSFETs
- 18 October 2016
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 63 (12), 4617-4623
- https://doi.org/10.1109/ted.2016.2614490
Abstract
As the physical sizes of devices have been scaled down, the negative impact of process-induced random variation on device performance has increased; therefore, there is an urgent demand for advanced simulation methods for variation. In this paper, a 3-D quasi-atomistic simulation methodology for line edge roughness (LER) in nonplanar devices, such as FinFETs and gate-all-around (GAA) FETs, is proposed. In addition, a simple gate oxide layer model is proposed to analyze the impact of LER on device performance while excluding the impact of oxide thickness variation. To verify the importance of the quasi-atomistic 3-D LER model and to compare the LER-induced performance variation in a FinFET to that in a GAA FET, the case studies using the 3-D quasi-atomistic LER model for FinFETs and GAA FETs are performed.Keywords
Funding Information
- Future Semiconductor Device Technology Development Program (10052925)
- Ministry of Trade, Industry, and Energy (MOTIE)
- Korea Semiconductor Research Consortium (KSRC)
- National Research Foundation of Korea (NRF)
- Korea government (MSIP) (2014R1A2A1A11050637)
This publication has 18 references indexed in Scilit:
- Worst Case Sampling Method with Confidence Ellipse for Estimating the Impact of Random Variation on Static Random Access Memory (SRAM)JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2015
- Performance and Variability of Doped Multithreshold FinFETs for 10-nm CMOSIEEE Transactions on Electron Devices, 2014
- Impact of random discrete dopant in extension induced fluctuation in gate–source/drain underlap FinFETJapanese Journal of Applied Physics, 2014
- Generating random rough edges, surfaces, and volumesApplied Optics, 2013
- Investigation of Nanowire Line-Edge Roughness in Gate-All-Around Silicon Nanowire MOSFETsIEEE Transactions on Electron Devices, 2010
- Impact of Line-Edge Roughness on Double-Gate Schottky-Barrier Field-Effect TransistorsIEEE Transactions on Electron Devices, 2009
- Impact of Stochastic Mismatch on Measured SRAM Performance of FinFETs with Resist/Spacer-Defined Fins: Role of Line-Edge-RoughnessPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2006
- Study of the evolution of nanoscale roughness from the line edge of exposed resist to the sidewall of deep-etched InP∕InGaAsP heterostructuresJournal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures, 2004
- Intrinsic threshold voltage fluctuations in decanano MOSFETs due to local oxide thickness variationsIEEE Transactions on Electron Devices, 2002
- Generalization of the Wiener-Khinchin theoremIEEE Signal Processing Letters, 1998