Investigation of Nanowire Line-Edge Roughness in Gate-All-Around Silicon Nanowire MOSFETs

Abstract

In this paper, the effects of nanowire line-edge roughness (LER) in gate-all-around silicon nanowire MOSFETs (SNWTs) are comprehensively investigated through 3-D statistical simulation. The LER impacts on both the device performance variation and mean value degradation are discussed in detail. Due to the unique nature of a nanowire structure, the LER in SNWTs contains two degrees of freedom, which allows the nanowire edges to vary in arbitrary transverse direction and which is different from the LER in traditional devices with one degree of freedom. In order to identify the relative importance of the diameter and center position variations, the nanowire LER can be considered as the combination of two basic types: One has a varied diameter with a fixed center (type A), and the other has a varied center position with a fixed diameter (type B). The results indicate the tradeoff between these two types of LER, with type A of a larger performance variation and type B of a larger performance degradation. Furthermore, as the gate length Lg shrinks below the correlation length Λ of the nanowire LER, the impacts from the source/drain extension region will dominate the variation. The impact of the main LER parameters is discussed for the scaled case with a non-Gaussian distribution in the device electrical parameters observed, and a new statistical method is proposed for better evaluation. On the other hand, the performance variation becomes insensitive to the correlation length in the case of Λ > L_g, which indicates a higher tolerance for the nanowire LER design in ultrascaled SNWTs. The optimized LER parameters are also given for the nanowire LER design with acceptable performance variation and suppressed mean value degradation in SNWTs.