SEU and SET Modeling and Mitigation in Deep Submicron Technologies

Abstract

As technology feature sizes decrease, single event upset (SEU), digital single event transient (DSET), and multiple bit upset (MBU) effects dominate the radiation response of microcircuits. Recent test circuits and test methods have quantified the pulse widths of DSETs generated from heavy-ion strikes on critical microcircuit nodes. These pulse widths have proven to be much larger than previously thought, which substantiates the importance of DSET induced errors to the soft error rate (SER) of modern microcircuits. New DSET circuit modeling approaches are presented which couple the circuit response to the charge collection mechanisms responsible for forming the DSET. These new circuit charge collection models successfully account for the experimentally observed heavy-ion induced transient widths and are supported by fully-coupled 3-d device physics simulations. Novel hardening and mitigation approaches are proposed based on our new understanding of the circuit response mechanisms. These new techniques are non-invasive to existing fabrication processes and can be transparently applied to existing bulk CMOS microcircuit layouts.