Heavy ion-induced digital single-event transients in deep submicron Processes
- 20 December 2004
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Nuclear Science
- Vol. 51 (6), 3480-3485
- https://doi.org/10.1109/tns.2004.839173
Abstract
Single-event transients (SETs) in digital circuits/processes are examined. SETs appear to substantially mitigate traditional SEU static-latch hardening techniques below 0.25 /spl mu/m. The resulting IC error rate for advanced technology node hardened-electronics is dominated by the combinational-logic SET rate.Keywords
This publication has 18 references indexed in Scilit:
- Modeling single-event effects in a complex digital deviceIEEE Transactions on Nuclear Science, 2003
- Laser-induced and heavy ion-induced single-event transient (SET) sensitivity measurements on 139-type comparatorsIEEE Transactions on Nuclear Science, 2002
- Critical charge for single-event transients (SETs) in bipolar linear circuitsIEEE Transactions on Nuclear Science, 2001
- Analysis of single-event effects in combinational logic-simulation of the AM2901 bitslice processorIEEE Transactions on Nuclear Science, 2000
- Upset hardened memory design for submicron CMOS technologyIEEE Transactions on Nuclear Science, 1996
- Microbeam studies of single-event effectsIEEE Transactions on Nuclear Science, 1996
- Dependence of the SEU window of vulnerability of a logic circuit on magnitude of deposited chargeIEEE Transactions on Nuclear Science, 1993
- Nuclear microprobe imaging of single-event upsetsIEEE Transactions on Nuclear Science, 1992
- Simulation of design dependent failure exposure levels for CMOS ICsIEEE Transactions on Nuclear Science, 1990
- A New Class of Single Event Soft ErrorsIEEE Transactions on Nuclear Science, 1984