Impact of Line-Edge Roughness on Double-Gate Schottky-Barrier Field-Effect Transistors
- 12 May 2009
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 56 (6), 1211-1219
- https://doi.org/10.1109/ted.2009.2017644
Abstract
The impact of line-edge roughness (LER) on double-gate (DG) Schottky-barrier field-effect transistors (SBFETs) in the level of device and circuit was investigated by a statistical simulation. The LER sequence is statistically generated by a Fourier analysis of the power spectrum of the Gaussian autocorrelation function. The results show that SBFETs are more sensitive to the LER effect in the high-V gs region and less sensitive in the subthreshold region compared with DG FinFETs. The aggressive fluctuation of drive current can be attributed to the variation of tunneling barrier width. Lowering the Schottky-barrier height and increasing the silicon-body thickness can suppress the parameter fluctuations from the LER effect. The simulation also shows that a 6T SRAM cell consisting of SBFETs is more vulnerable to noise disturbance than its counterpart consisting of FinFETs, particularly for the read operation, which is due to a larger mismatch of drivability of SBFETs within the cell.Keywords
This publication has 43 references indexed in Scilit:
- A Comparative Study of Dopant-Segregated Schottky and Raised Source/Drain Double-Gate MOSFETsIEEE Transactions on Electron Devices, 2008
- Impact of LER and Random Dopant Fluctuations on FinFET Matching PerformanceIEEE Transactions on Nanotechnology, 2008
- Impact of Line-Edge Roughness on FinFET Matching PerformanceIEEE Transactions on Electron Devices, 2007
- Comparison study of tunneling models for Schottky field effect transistors and the effect of Schottky barrier loweringIEEE Transactions on Electron Devices, 2006
- Impact of Stochastic Mismatch on Measured SRAM Performance of FinFETs with Resist/Spacer-Defined Fins: Role of Line-Edge-RoughnessPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2006
- A Comparison Study of Symmetric Ultrathin-Body Double-Gate Devices With Metal Source/Drain and Doped Source/DrainIEEE Transactions on Electron Devices, 2005
- Schottky-Barrier S/D MOSFETs With High-$Kappa$Gate Dielectrics and Metal-Gate ElectrodeIEEE Electron Device Letters, 2004
- A 50-nm-gate-length erbium-silicided n-type Schottky barrier metal-oxide-semiconductor field-effect transistorApplied Physics Letters, 2004
- Intrinsic parameter fluctuations in decananometer mosfets introduced by gate line edge roughnessIEEE Transactions on Electron Devices, 2003
- Device scaling limits of Si MOSFETs and their application dependenciesProceedings of the IEEE, 2001