A framework for low power synthesis of interconnection networks-on-chip with multiple voltage islands
- 30 June 2012
- journal article
- Published by Elsevier BV in Integration
- Vol. 45 (3), 271-281
- https://doi.org/10.1016/j.vlsi.2011.11.010
Abstract
No abstract availableKeywords
This publication has 14 references indexed in Scilit:
- Efficient mapping and voltage islanding technique for energy minimization in NoC under design constraintsPublished by Association for Computing Machinery (ACM) ,2010
- NoC topology synthesis for supporting shutdown of voltage islands in SoCsPublished by Association for Computing Machinery (ACM) ,2009
- Energy-Aware Synthesis of Networks-on-Chip Implemented with Voltage IslandsProceedings of the 39th conference on Design automation - DAC '02, 2007
- An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOSIEEE International Solid-State Circuits Conference, 2007
- Designing Application-Specific Networks on Chips with Floorplan Information2006 IEEE/ACM International Conference on Computer Aided Design, 2006
- Hardware based frequency/voltage control of voltage frequency island systemsPublished by Association for Computing Machinery (ACM) ,2006
- A Low Complexity Heuristic for Design of Custom Network-on-Chip ArchitecturesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2006
- Standby and Active Leakage Current Control and Minimization in CMOS VLSI CircuitsIEICE Transactions on Electronics, 2005
- A low-latency FIFO for mixed-clock systemsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Managing power and performance for System-on-Chip designs using Voltage Islands2006 IEEE/ACM International Conference on Computer Aided Design, 2002