A low-latency FIFO for mixed-clock systems
- 7 November 2002
- conference paper
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableThis publication has 4 references indexed in Scilit:
- A methodology for correct-by-construction latency insensitive designPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Pausible clocking: a first step toward heterogeneous systemsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Pipeline synchronizationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Asynchronous wrapper for heterogeneous systemsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002