A Dominating Error Region Strategy for Improving the Bit-Flipping LDPC Decoder of SSDs

Abstract

This brief presents a dominating error region strategy (DERS) that improves the bit-flipping (BF) low-density parity-check decoder for solid-state drives. With the help of the DERS, the state-of-the-art BF decoding algorithms achieve better error correction performance while taking less iterations. Specifically, the DERS provides solutions for restricting the occurrences of an even number of flipped bits and bit-error propagations, both of which are intrinsic problems to current BF decoding algorithms. The DERS can be implemented with a simple circuitry and serve as a fine-tuning technique for the decoding reliability-performance tradeoff. In this brief, the DERS is evaluated with numerical analysis and computer simulations.