High-Performance 15-V Novel LDMOS Transistor Architecture in a 0.25- $\mu\hbox{m}$ BiCMOS Process for RF-Power Applications
- 2 April 2007
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 54 (4), 861-868
- https://doi.org/10.1109/ted.2007.892355
Abstract
The optimization of the small and large signal performances of a radio frequency (RF)-LDMOS is presented via the achievement of a novel LDMOS architecture. Specific process steps are introduced into a 0.25-mum BiCMOS technology and precisely described to realize a fully salicided gate RF-LDMOS architecture. Significant improvement is obtained on the small-signal - fT and Fmax - and power performances while maintaining good dc characteristicsKeywords
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