Assessment of InAs/AlGaSb Tunnel-FET Virtual Technology Platform for Low-Power Digital Circuits
- 23 May 2016
- journal article
- research article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 63 (7), 2749-2756
- https://doi.org/10.1109/ted.2016.2566614
Abstract
In this work, a complementary InAs/Al 0.05 Ga 0.95 Sb tunnel field-effect-transistor (TFET) virtual technology platform is benchmarked against the projection to the CMOS FinFET 10-nm node, by means of device and basic circuit simulations. The comparison is performed in the ultralow voltage regime (below 500 mV), where the proposed III-V TFETs feature ON-current levels comparable to scaled FinFETs, for the same low-operating-power OFF-current. Due to the asymmetrical n- and p-type I-Vs, trends of noise margins and performances are investigated for different Wp/Wn ratios. Implications of the device threshold voltage variability, which turned out to be dramatic for steep slope TFETs, are also addressed.Keywords
Funding Information
- European Community’s Seventh Framework Programme through the Project E2SWITCH (619509)
This publication has 31 references indexed in Scilit:
- First foundry platform of complementary tunnel-FETs in CMOS baseline technology for ultralow-power IoT applications: Manufacturability, variability and technology roadmapPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2015
- III-V Heterostructure Nanowire Tunnel FETsIEEE Journal of the Electron Devices Society, 2015
- Design of Low Voltage Tunneling-FET Logic Circuits Considering Asymmetric Conduction CharacteristicsIEEE Journal on Emerging and Selected Topics in Circuits and Systems, 2014
- Comprehensive study of effective current variability and MOSFET parameter correlations in 14nm multi-fin SOI FINFETsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2013
- Tunnel transistors for energy efficient computingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2013
- Design and Analysis of Robust Tunneling FET SRAMIEEE Transactions on Electron Devices, 2013
- Exploring sub-20nm FinFET design with predictive technology modelsPublished by Association for Computing Machinery (ACM) ,2012
- On the gate-stack origin threshold voltage variability in scaled FinFETs and multi-FinFETsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2010
- Analysis and comparison on full adder block in submicron technologyIEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2002
- A voltage reduction technique for digital systemsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1990