A voltage reduction technique for digital systems

Abstract

A self-regulating on-chip voltage-reduction circuit that adjusts the internal supply voltage to the lowest value compatible with chip speed requirements is described. Besides enhancing reliability, this technique allows power savings. The technique is based on regulation of the supply voltage of an equivalent critical path, a small circuit with delay V/sub dd/ properties proportional to those of the actual critical path. The output of this equivalent critical path is compared with the output of a second identical equivalent critical path which is connected to the full supply voltage and serves as a reference. In a first-order approximation the ratio of the delay of a critical path to the period of a ring oscillator is a constant that depends only on the number of gates, the dimensions of the transistors, and the load capacitances. This means that a ring oscillator can be used as an equivalent critical path for all digital circuits. Moreover, when the supply voltage of a ring oscillator (VCO) is changed the frequency changes. The voltage regulator principle can be implemented with a phase-locked loop (PLL). By adjusting the VCO supply voltage, the PLL causes the VCO to oscillate at N*f/sub in/. If the dimensions of the VCO transistors and the division ratio N are such that the critical path functions correctly at the regulated voltage, it will always function correctly, as changing parameters temperature or frequency f/sub in/ affect the VCO in the same way as the circuitry.<>