A Reduced-sp- $$\hbox {D3L}_{\mathrm{sum}}$$ D3L sum Adder-Based High Frequency $$4\times 4$$ 4 × 4 Bit Multiplier Using Dadda Algorithm
- 24 November 2015
- journal article
- Published by Springer Science and Business Media LLC in Circuits, Systems, and Signal Processing
- Vol. 35 (9), 3113-3134
- https://doi.org/10.1007/s00034-015-0201-7
Abstract
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