Low power and high speed multiplier design with row bypassing and parallel architecture
- 31 October 2010
- journal article
- Published by Elsevier BV in Microelectronics Journal
- Vol. 41 (10), 639-650
- https://doi.org/10.1016/j.mejo.2010.06.009
Abstract
No abstract availableKeywords
This publication has 16 references indexed in Scilit:
- A novel low-power full-adder cell with new technique in designing logical gates based on static CMOS inverterMicroelectronics Journal, 2009
- Low power multipliers based on new hybrid full addersMicroelectronics Journal, 2008
- Low-Power Multiplier Design Using a Bypassing TechniqueJournal of Signal Processing Systems, 2008
- Design of a low-power, high performance, 8×8bit multiplier using a Shannon-based adder cellMicroelectronics Journal, 2008
- A micropower low-voltage multiplier with reduced spurious switchingIEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2005
- High-speed and low-power split-radix FFTIEEE Transactions on Signal Processing, 2003
- A low-power array multiplier using separated multiplication techniqueIEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 2001
- Multiplexer-based array multipliersInternational Conference on Acoustics, Speech, and Signal Processing (ICASSP), 1999
- Low-power CMOS digital designIEEE Journal of Solid-State Circuits, 1992
- A Suggestion for a Fast MultiplierIEEE Transactions on Electronic Computers, 1964