A high-speed asynchronous array multiplier based on multi-threshold semi-static NULL convention logic pipeline

Abstract

This paper proposes an asynchronous 12 × 12 -bit array multiplier. Firstly, we proposed a new asynchronous pipeline of which data processing and completion detection can be carried out simultaneously by applying multi-threshold semi-static NCL (MTSNCL) to asynchronous combinational logic. Sencondly, the pipeline is used for designing an asynchronous 12 × 12 -bit array multiplier. Finally, both the proposed array multiplier and the original array multiplier are simulated based on SMIC 0.18-μm CMOS technology. Compared with the general asynchronous array multiplier, the new array multiplier has 76.5% higher throughput, 43.8% lower T DD cycle time and 38.7% lower static power consumption. The multi-threshold array multiplier is suitable for high-speed lower-power asynchronous multiplier design.