An Experimental Study of N-Detect Scan ATPG Patterns on a Processor
- 10 June 2004
- conference paper
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
This paper studies the impact of N-detect scan ATPGpatterns on test quality and associated test costs. Anincremental method for test generation is presented.Metrics to evaluate the richness of the test set arepresented. The natural N-detect profiles of regular one-detecttest sets and the impact to test data volume and testtime of generating additional patterns is studied. Resultsare presented on an Intel® Pentium® 4 processor.Simulation results from evaluating the patterns on layoutextracted and random bridges are presented. Silicon datafrom production test shows the effectiveness of N-detecttests.Keywords
This publication has 13 references indexed in Scilit:
- Impact of multiple-detect test patterns on product qualityPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2004
- Analyzing the effectiveness of multiple-detect test setsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2004
- Experimental evaluation of scan tests for bridgesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Extraction and simulation of realistic CMOS faults using inductive fault analysisPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Stuck-at tuple-detection: a fault model based on stuck-at faults for improved defect coveragePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- On n-detection test sequences for synchronous sequential circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- An experimental study comparing the relative effectiveness of functional, scan, IDDq and delay-fault testingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Stuck-fault tests vs. actual defectsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Defect-oriented testing and defective-part-level predictionIEEE Design & Test of Computers, 2001
- A novel algorithm to extract two-node bridgesPublished by Association for Computing Machinery (ACM) ,2000