Experimental evaluation of scan tests for bridges
- 25 June 2003
- conference paper
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
An impressive body of theoretical research to model the behavior of bridges exists. We take that a step further and describe an experiment to compute single cycle scan tests for bridges and evaluate them in silicon. Experimental data, on a high volume part, shows that by marginally increasing the static bridge fault coverage of realistic bridges, unique parts missed by a comprehensive set of stuck-at tests were detected. We believe that this is the first silicon data on the value of adding single cycle scan tests for bridges to the manufacturing flow.Keywords
This publication has 12 references indexed in Scilit:
- AN ACCURATE BRIDGING FAULT TEST PATTERN GENERATORPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- Test Pattern Generation for Realistic Bridge Faults in CMOS ICsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- Fault models for speed failures caused by bridges and opensPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A comparison of bridging fault simulation methodsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Extraction and simulation of realistic CMOS faults using inductive fault analysisPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Carafe: an inductive fault analysis tool for CMOS VLSI circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Biased voting: A method for simulating CMOS bridging faults in the presence of variable gate logic thresholdsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Testing CMOS logic gates for: realistic shortsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- BART: a bridging fault test generator for sequential circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A scalable and efficient methodology to extract two node bridges from large industrial circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002