Handling shared variable synchronization in multi-core Network-on-Chips with distributed memory
- 1 September 2010
- conference paper
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE) in 23rd IEEE International SOC Conference
Abstract
Parallelized shared variable applications running on multi-core Network-on-Chips (NoCs) require efficient support for synchronization, since communication is on the critical path of system performance and contended synchronization requests may cause large performance penalty. In this paper, we propose a dedicated hardware module for synchronization management. This module is called Synchronization Handler (SH), integrated with each processor-memory node on the multi-core NoCs. It uses two physical buffers to concurrently process synchronization requests issued by the local processor and remote processors via the on-chip network. One salient feature is that the two physical buffers are dynamically allocated to form multiple virtual buffers (a virtual buffer is related to a shared synchronization variable) so as to improve the buffer utilization and alleviate the head-of-line blocking. Synthesis results suggest that the SH can run over 900 MHz in 130nm technology with small area overhead. To justify the SH-enhanced multicore NoCs, we employ synthetic workloads to evaluate synchronization cost and buffer utilization, and run synchronization-intensive applications to investigate speedup. The results show that our approach is viable.Keywords
This publication has 9 references indexed in Scilit:
- Efficiency and scalability of barrier synchronization on NoC based many-core architecturesPublished by Association for Computing Machinery (ACM) ,2008
- Distributed and low-power synchronization architecture for embedded multiprocessorsPublished by Association for Computing Machinery (ACM) ,2008
- Synchronization state bufferPublished by Association for Computing Machinery (ACM) ,2007
- Efficient Synchronization for Embedded On-Chip MultiprocessorsIEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2006
- A survey of research and practices of Network-on-chipACM Computing Surveys, 2006
- Power/Performance Hardware Optimization for Synchronization Intensive Applications in MPSoCsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2006
- Fast synchronization for chip multiprocessorsACM SIGARCH Computer Architecture News, 2005
- Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect ArchitecturesIEEE Transactions on Computers, 2005
- Networks on ChipPublished by Springer Science and Business Media LLC ,2003