Fast synchronization for chip multiprocessors
- 1 November 2005
- journal article
- Published by Association for Computing Machinery (ACM) in ACM SIGARCH Computer Architecture News
- Vol. 33 (4), 64-69
- https://doi.org/10.1145/1105734.1105743
Abstract
This paper presents a novel mechanism for barrier synchronization on chip multi-processors (CMPs). By forcing the invalidation of selected I-cache lines, this mechanism starves threads and thus forces their execution to stop. Threads are let free when all have entered the barrier.We evaluated this mechanism using SMTSim and report much better (and most importantly, more flat) performance than lock-based barriers supported by existing microprocessors.Keywords
This publication has 8 references indexed in Scilit:
- High-Performance Throughput ComputingIEEE Micro, 2005
- Niagara: A 32-Way Multithreaded Sparc ProcessorIEEE Micro, 2005
- Packaging the Blue Gene/L supercomputerIBM Journal of Research and Development, 2005
- Design and implementation of message-passing services for the Blue Gene/L supercomputerIBM Journal of Research and Development, 2005
- Multicores from the compiler's perspective: a blessing or a curse?Published by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- IBM power5 chip: a dual-core multithreaded processorIEEE Micro, 2004
- The network architecture of the Connection Machine CM-5 (extended abstract)Published by Association for Computing Machinery (ACM) ,1992
- Algorithms for scalable synchronization on shared-memory multiprocessorsACM Transactions on Computer Systems, 1991