A Multi-Level-Cell Bipolar-Selected Phase-Change Memory
- 1 February 2008
- conference paper
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE International Solid-State Circuits Conference
- No. 01936530,p. 428-625
- https://doi.org/10.1109/isscc.2008.4523240
Abstract
Phase-change memory (PCM) is becoming widely recognized as the most likely candidate to unify the many memory technologies that exist today (Lee, et al., 2007). The combination of non-volatile attributes of flash, RAM-like bit-alterability, and fast reads and writes position PCM to enable changes in the memory subsystems of cellular phones, PCs and countless embedded and consumer electronics applications. This design's multi-level cell (MLC) capabilities combined with long- term scalability reduce PCM costs as only realized before by hard disk drives. MLC technology is challenged with fitting more cell states (4 in the case of 2 bit per cell), along with distribution spreads due to process, design, and environmental variations, within a limited window. We describe a 256Mb MLC test-chip in a 90nm micro-trench (mutrench) PCM technology, and MLC endurance results from an 8Mb 0.18mum PCM test-chip with the same trench cell structure. A program algorithm achieving tightly placed inner states and experimental results illustrating distinct current distributions are presented to demonstrate MLC capability.Keywords
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