SurfNoC
- 23 June 2013
- conference paper
- conference paper
- Published by Association for Computing Machinery (ACM) in Proceedings of the 40th Annual International Symposium on Computer Architecture
- Vol. 41 (3), 583-594
- https://doi.org/10.1145/2485922.2485972
Abstract
As multicore processors find increasing adoption in domains such as aerospace and medical devices where failures have the potential to be catastrophic, strong performance isolation and security become first-class design constraints. When cores are used to run separate pieces of the system, strong time and space partitioning can help provide such guarantees. However, as the number of partitions or the asymmetry in partition bandwidth allocations grows, the additional latency incurred by time multiplexing the network can significantly impact performance. In this paper, we introduce SurfNoC, an on-chip network that significantly reduces the latency incurred by temporal partitioning. By carefully scheduling the network into waves that flow across the interconnect, data from different domains carried by these waves are strictly non-interfering while avoiding the significant overheads associated with cycle-by-cycle time multiplexing. We describe the scheduling policy and router microarchitecture changes required, and evaluate the information-flow security of a synthesizable implementation through gate-level information flow analysis. When comparing our approach for varying numbers of domains and network sizes, we find that in many cases SurfNoC can reduce the latency overhead of implementing cycle-level non-interference by up to 85%.Keywords
This publication has 33 references indexed in Scilit:
- F6COM: A component model for resource-constrained and dynamic space-based computing environmentsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2013
- Enhancing the security of time-division-multiplexing networks-on-chip through the use of multipath routingPublished by Association for Computing Machinery (ACM) ,2011
- Fault containment in a reconfigurable Multi-Processor System-on-a-ChipPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2011
- Topology-Aware Quality-of-Service Support in Highly Integrated Chip MultiprocessorsLecture Notes in Computer Science, 2011
- CoMPSoCACM Transactions on Design Automation of Electronic Systems, 2009
- Yet another MicroArchitectural Attack:Published by Association for Computing Machinery (ACM) ,2007
- Predicting Secret Keys Via Branch PredictionLecture Notes in Computer Science, 2006
- Æthereal Network on Chip:Concepts, Architectures, and ImplementationsIEEE Design & Test of Computers, 2005
- Security wrappers and power analysis for SoC technologyPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2004
- Security wrappers and power analysis for SoC technologiesPublished by Association for Computing Machinery (ACM) ,2003