A fast and well-structured multiplier
- 1 January 2004
- conference paper
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 508-515
- https://doi.org/10.1109/dsd.2004.1333319
Abstract
The performance of multiplication is crucial for multimedia applications such as 3D graphics and signal processing systems which depend on extensive numbers of multiplications. Previously reported multiplication algorithms mainly focus on rapidly reducing the partial products rows down to final sums and carries used for the final accumulation. These techniques mostly rely on circuit optimization and minimization of the critical paths. In this paper, an algorithm to achieve fast multiplication in two's complement representation is presented. Indeed, our approach focuses on reducing the number of partial product rows. In turn, this directly influences the speed of the multiplication, even before applying partial products reduction techniques. Fewer partial products rows are produced, thereby lowering the overall operation time. This results in a true diamond-shape for the partial product tree which is more efficient in terms of implementation.Keywords
This publication has 16 references indexed in Scilit:
- Analysis of Booth encoding efficiency in parallel multipliers using compressors for reduction of partial productsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Measuring the performance of multimedia instruction setsIEEE Transactions on Computers, 2002
- A 600-MHz 54×54-bit multiplier with rectangular-styled Wallace treeIEEE Journal of Solid-State Circuits, 2001
- High-speed Booth encoded parallel multiplier designIEEE Transactions on Computers, 2000
- Optimal circuits for parallel multipliersIEEE Transactions on Computers, 1998
- A method for speed optimized partial product reduction and generation of fast parallel multipliers using an algorithmic approachIEEE Transactions on Computers, 1996
- A 15-ns 32*32-b CMOS multiplier with an improved parallel structureIEEE Journal of Solid-State Circuits, 1990
- On Multiple Operand Addition of Signed Binary NumbersIEEE Transactions on Computers, 1978
- A Suggestion for a Fast MultiplierIEEE Transactions on Electronic Computers, 1964
- High-Speed Arithmetic in Binary ComputersProceedings of the IRE, 1961