Analysis of Booth encoding efficiency in parallel multipliers using compressors for reduction of partial products
- 30 December 2002
- conference paper
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
Booth encoding method is evaluated in this paper. amount of logic of a properly connected (3,2) counter will Although generally used in parallel multipliers, we show this scheme to be obsolete due to the improvements in bit compression trees. The number of gate levels with and without Booth encodin2 is comvared when 4:2 is implemented. compressors are used. It was found that a single row of 4:2 compressors reduces the number of partial products 2. Booth-Maaorley recoding to one ha& which is the essential function of the Booth encoding technique. We have found that a single row of 4:2 compressors achieves this reduction in less time and with fewer gates used. The case of 2's complement representation is discussedKeywords
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