2 × VDD output buffer with 36.4% slew rate improvement using leakage current compensation
Open Access
- 1 January 2017
- journal article
- circuits and-systems
- Published by Institution of Engineering and Technology (IET) in Electronics Letters
- Vol. 53 (2), 62-64
- https://doi.org/10.1049/el.2016.2351
Abstract
A 2 × VDD output buffer using leakage current compensation is demonstrated. With the proposed leakage current compensation circuit, the SR (slew rate) is improved 36.4–101.89% based on on-silicon measurement results given different VDDIO (1.0/1.2/1.8 V) and temperatures (from 0 to 100°C). The data rate is 510/630/400 MHz for VDDIO at 1.8/1.2/1.0 V, respectively. Moreover, the reliability problem, the gate oxide overstress and the hot carrier degradation is avoided. The proposed design is implemented using a typical 90 nm CMOS process. The active area is 0.425 × 0.0563 mm. The SR is measured in the range from 0.766 to 2.585 V/ns.Keywords
This publication has 6 references indexed in Scilit:
- Design of $2 \times {\rm V}_{\rm DD}$-Tolerant I/O Buffer With PVT Compensation Realized by Only $1 \times {\rm V}_{\rm DD}$ Thin-Oxide DevicesIEEE Transactions on Circuits and Systems I: Regular Papers, 2013
- Power-Rail ESD Clamp Circuit With Diode-String ESD Detection to Overcome the Gate Leakage Current in a 40-nm CMOS ProcessIEEE Transactions on Electron Devices, 2013
- On-Chip Process and Temperature Monitor for Self-Adjusting Slew Rate Control of 2$\,\times\,$VDD Output BuffersIEEE Transactions on Circuits and Systems I: Regular Papers, 2013
- An Efficient Technique for Leakage Current Estimation in Nanoscaled CMOS Circuits Incorporating Self-Loading EffectsIEEE Transactions on Computers, 2010
- A $\hbox{Gb/s}+$ Slew-Rate/Impedance-Controlled Output Driver With Single-Cycle Compensation TimeIEEE Transactions on Circuits and Systems II: Express Briefs, 2010
- Slew-Rate-Controlled Output Driver Having Constant Transition Time Over Process, Voltage, Temperature, and Output Load VariationsIEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 2007