Design of $2 \times {\rm V}_{\rm DD}$-Tolerant I/O Buffer With PVT Compensation Realized by Only $1 \times {\rm V}_{\rm DD}$ Thin-Oxide Devices
- 25 September 2013
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Circuits and Systems I: Regular Papers
- Vol. 60 (10), 2549-2560
- https://doi.org/10.1109/tcsi.2013.2244351
Abstract
A new 2×VDD-tolerant input/output (I/O) buffer with process, voltage, and temperature (PVT) compensation is proposed and verified in a 90-nm CMOS process. Consisting of the dynamic source bias and gate controlled technique, the proposed mixed-voltage I/O buffer realized by only 1 xVDD devices can successfully transmit and receive 2×VDD signal. Utilizing this technique with only 1 xVDD devices, the digital logic gates are also modified to have 2 xVDD-tolerant capability. With 2 VDD-tolerant logic gates, the PVT variation detector has been implemented to detect PVT variations from 2×VDD signal and provide compensation control to the 2×VDD-tolerant I/O buffer without suffering the gate-oxide overstress issue.Keywords
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