Design of SRAM PUF with improved uniformity and reliability utilizing device aging effect
- 1 June 2014
- conference paper
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE) in 2014 IEEE International Symposium on Circuits and Systems (ISCAS)
- p. 1941-1944
- https://doi.org/10.1109/iscas.2014.6865541
Abstract
SRAM Physical Unclonable Function (PUF) makes use of efficient silicon fabrication process where duplication of exact replica devices is difficult. One of the major issues with SRAM-PUF is the reliability and uniformity of the start-up pattern with environmental fluctuations. This paper presents a technique for improving uniformity (distribution of 1's & 0's) and reliability (variations in power-up patterns) of SRAM-PUF utilizing aging effects (mainly NBTI). The proposed technique maintains the uniformity of SRAM-PUF by controlling the polarity of the aging in SRAM arrays. The reliability is controlled by further injecting aging to the SRAM arrays after achieving target uniformity.Keywords
This publication has 7 references indexed in Scilit:
- Evaluation of 90nm 6T-SRAM as Physical Unclonable Function for secure key generation in wireless sensor nodesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2011
- A soft decision helper data algorithm for SRAM PUFsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2009
- Power-Up SRAM State as an Identifying Fingerprint and Source of True Random NumbersIEEE Transactions on Computers, 2008
- Brand and IP protection with physical unclonable functionsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2008
- Turning liabilities into assets: Exploiting deep submicron CMOS technology to design secure embedded circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2008
- Product Burn-in Stress Impacts on SRAM Array PerformancePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2007
- Extracting secret keys from integrated circuitsIEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2005