Product Burn-in Stress Impacts on SRAM Array Performance

Abstract

Product burn-in stresses are commonly performed on SRAM array to accelerate transistor failure mechanism and screen out weak SRAM cells. For sub-100 nm technology, the possible impacts from burn-in stress are negative bias temperature instability (NBTI) (Schroder and Babcock, 2003) on PFET and hot carrier effect (HCE) on NFET. Recently several groups (Muller et al., 2004 and LaRosa et al., 2006) reported the studies of NBTI impact on SRAM array performance, either using circuit simulation (Muller et al., 2004) or based on test results of discrete SRAM cell (LaRosa et al., 2006). Our study, for the first time, is directly based on the product results from burn-in stress on SRAM array. With device reliability models and circuit simulation, we analyzed the shift of key product parameters: SRAM array stand-by current (Iddq) and minimum array operation voltage (Vcsmin). Our studies show that PFET NBTI is the dominant factor that is responsible for the degradation of SRAM array stability, and its impact on Vcsmin is predictable by Iddq data and modeling.