A study of the threshold voltage variation for ultra-small bulk and SOI CMOS

Abstract

This paper addresses the scalability of bulk CMOS, and the feasibility of intrinsic channel SOI (IC-SOI) CMOS, as an alternative to the bulk, in view of the threshold voltage (V/sub TH/) fluctuations. The impact of dopant-induced V/sub TH/ variations on bulk CMOS SRAM operation is evaluated using a newly proposed analytical method. It is estimated that the bulk SRAM performance will be seriously degraded as the channel length approaches 25-30 nm even if an elaborate redundancy scheme is used. For the IC-SOI FETs, instead of the dopant fluctuations, silicon thickness variation is a critical issue. However, systematic simulation results show that, by optimizing the FET design, the thickness-induced V/sub TH/ variations for both planar single gate and vertical double gate 25 mm IC-SOI FETs will be acceptable, assuming a reasonable thickness deviation range. Therefore, the IC-SOI CMOS is expected to be superior to the bulk counterpart at L=25 nm. It was also found that optimizing the back bias is necessary for suppressing the V/sub TH/ variations of the single gate IC-SOI FETs.