Bonded planar double-metal-gate NMOS transistors down to 10 nm
- 2 May 2005
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Electron Device Letters
- Vol. 26 (5), 317-319
- https://doi.org/10.1109/led.2005.846580
Abstract
Thanks to bonding, metal-gate etching without any out-of-gate Si consumption, and self-aligned transfer of alignment marks, we have processed the first 10-nm-gate-length DG MOS transistors with metal gates. These devices exhibit excellent short-channel effects control and high-performance characteristics. Their saturation current is very sensitive to the access resistance increase caused by film thinning required to respect the scaling rules. Moreover, their electrical properties can be tuned between LSTP and HP by independently biasing the two gates.Keywords
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