Locally strained ultra-thin channel 25nm narrow FDSOI devices with metal gate and mesa isolation

Abstract

Strained silicon devices offer very high carrier mobility. If we put them on an SOI substrate we also improve short-channel control and junction leakage. In this paper, we present a new approach to introducing strain in very thin silicon layers. NMOS and PMOS CV/I performance of 0.2 ps and 0.3 ps, respectively, is the highest reported. We analyze 3D geometrical effects on stress, mobility, and drive currents using the 3D process and device simulator, Taurus.