A QoS-aware memory controller for dynamically balancing GPU and CPU bandwidth use in an MPSoC
- 3 June 2012
- conference paper
- conference paper
- Published by Association for Computing Machinery (ACM) in Proceedings of the 49th Annual Design Automation Conference on - DAC '12
- p. 850-855
- https://doi.org/10.1145/2228360.2228513
Abstract
No abstract availableKeywords
This publication has 9 references indexed in Scilit:
- The gem5 simulatorACM SIGARCH Computer Architecture News, 2011
- Rank based dynamic voltage and frequency scaling fortiled graphics processorsPublished by Association for Computing Machinery (ACM) ,2010
- A Hybrid DVS Scheme for Interactive 3D GamesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2008
- PredatorPublished by Association for Computing Machinery (ACM) ,2007
- Process Variation Tolerant 3T1D-Based Cache ArchitecturesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2007
- Fair Queuing Memory SystemsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2006
- MinneSPEC: A New SPEC Benchmark Workload for Simulation-Based Computer Architecture ResearchIEEE Computer Architecture Letters, 2002
- A permutation-based page interleaving scheme to reduce row-buffer conflicts and exploit data localityPublished by Association for Computing Machinery (ACM) ,2000
- Memory access schedulingPublished by Association for Computing Machinery (ACM) ,2000