Fair Queuing Memory Systems
- 1 December 2006
- conference paper
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE) in 2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06)
- p. 208-222
- https://doi.org/10.1109/micro.2006.24
Abstract
We propose and evaluate a multi-thread memory scheduler that targets high performance CMPs. The proposed memory scheduler is based on concepts originally developed for network fair queuing scheduling algorithms. The memory scheduler is fair and provides quality of service (QoS) while improving system performance. On a four processor CMP running workloads containing a mix of applications with a range of memory bandwidth demands, the proposed memory scheduler provides QoS to all of the threads in all of the workloads, improves system performance by an average of 14% (41% in the best case), and reduces the variance in the threads' target memory bandwidth utilization from .2 to .0058Keywords
This publication has 15 references indexed in Scilit:
- Memory Controller Optimizations for Web ServersPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- An efficient quality-aware memory controller for multimedia platform SoCIEEE Transactions on Circuits and Systems for Video Technology, 2005
- A study of performance impact of memory controller features in multi-processor server environmentPublished by Association for Computing Machinery (ACM) ,2004
- A performance comparison of contemporary DRAM architecturesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Scheduling for quality of service guarantees via service curvesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Asim: a performance model frameworkComputer, 2002
- Concurrency, latency, or system overheadPublished by Association for Computing Machinery (ACM) ,2001
- Memory bandwidth limitations of future microprocessorsPublished by Association for Computing Machinery (ACM) ,1996
- A generalized processor sharing approach to flow control in integrated services networks: the single-node caseIEEE/ACM Transactions on Networking, 1993
- Some Results of the Earliest Deadline Scheduling AlgorithmIEEE Transactions on Software Engineering, 1989