On Manufacturing Aware Physical Design to Improve the Uniqueness of Silicon-Based Physically Unclonable Functions

Abstract

Physically Unclonable Functions (PUFs) are hardware cryptographic primitives for generating unique signatures from complex and irreproducible manufacturing variations. The uniqueness of a PUF is a fundamental performance metric that defines the extent to which a response is tied to a single device. It is often compromised if the manufacturing variations are suppressed. Though attempts have been made to improve the quality of a PUF at system level, very little work has been done at enhancing the impact of manufacturing variations on PUF circuits. In this work, we propose a novel generalized systematic framework for improving inter-die and inter-wafer manufacturing variations of a PUF circuit. The framework aligns the gate structures at pitches closer to forbidden zone, where the sensitivity of Critical Dimension (CD) to the pitch variations is very high. We validated the proposed technique using a large population sample of arbiter PUFs. Simulation results show that the proposed scheme has improved inter-die and inter-wafer uniqueness of arbiter PUFs by as much as 8.4% and 16% respectively. The framework can be applied to any delay-based silicon PUF structure.