A novel Si tunnel FET with 36mV/dec subthreshold slope based on junction depleted-modulation through striped gate configuration
- 1 December 2012
- conference paper
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 8.5.1-8.5.4
- https://doi.org/10.1109/iedm.2012.6479005
Abstract
In this paper, a novel junction depleted-modulation design to achieve equivalently abrupt tunnel junction of Si Tunnel FET (TFET) is proposed. By changing the gate layout configuration, the new Junction-modulated TFET can reliably and effectively achieve much steeper switching behavior and higher ON current without area penalty and special fabrication compared with traditional TFET. Further junction optimization by introducing the self-depleted doping pocket with much relaxed process requirements is also experimentally demonstrated based on the bulk Si substrate. With traditional Si CMOS-compatible process, the fabricated device shows a minimum substhreshold slope of 36mV/dec within one decade of drain current.Keywords
This publication has 2 references indexed in Scilit:
- Silicon Nanowire Tunneling Field-Effect Transistor Arrays: Improving Subthreshold Performance Using Excimer Laser AnnealingIEEE Transactions on Electron Devices, 2011
- Effect of Pocket Doping and Annealing Schemes on the Source-Pocket Tunnel Field-Effect TransistorIEEE Transactions on Electron Devices, 2010