On the detection of delay faults
- 6 January 2003
- conference paper
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableThis publication has 6 references indexed in Scilit:
- On path selection in combinational logic circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Random pattern testability of delay faultsIEEE Transactions on Computers, 1988
- On Delay Fault Testing in Logic CircuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1987
- Modeling and Testing for Timing Faults in Synchronous Sequential CircuitsIEEE Design & Test of Computers, 1984
- An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic CircuitsIEEE Transactions on Computers, 1981
- An Experimental Delay Test Generator for LSI LogicIEEE Transactions on Computers, 1980