On path selection in combinational logic circuits
- 6 January 2003
- conference paper
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableThis publication has 6 references indexed in Scilit:
- Random pattern testability of delay faultsIEEE Transactions on Computers, 1988
- On Delay Fault Testing in Logic CircuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1987
- Modeling and Testing for Timing Faults in Synchronous Sequential CircuitsIEEE Design & Test of Computers, 1984
- Timing Verification and the Timing Analysis programPublished by Association for Computing Machinery (ACM) ,1982
- Synchronous path analysis in MOS circuit simulatorPublished by Association for Computing Machinery (ACM) ,1982
- Timing Analysis of Computer HardwareIBM Journal of Research and Development, 1982