On Delay Fault Testing in Logic Circuits
- 1 September 1987
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Vol. 6 (5), 694-703
- https://doi.org/10.1109/tcad.1987.1270315
Abstract
No abstract availableThis publication has 8 references indexed in Scilit:
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- Modeling and Testing for Timing Faults in Synchronous Sequential CircuitsIEEE Design & Test of Computers, 1984
- Random Pattern TestabilityIEEE Transactions on Computers, 1984
- Timing Analysis of Computer HardwareIBM Journal of Research and Development, 1982
- An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic CircuitsIEEE Transactions on Computers, 1981
- An Experimental Delay Test Generator for LSI LogicIEEE Transactions on Computers, 1980
- Probabilistic Treatment of General Combinational NetworksIEEE Transactions on Computers, 1975
- Diagnosis of Automata Failures: A Calculus and a MethodIBM Journal of Research and Development, 1966