Thermal resistance optimization of GaN/substrate stacks considering thermal boundary resistance and temperature-dependent thermal conductivity

Abstract

Here, we investigate the effects of thermal boundary resistance (TBR) and temperature-dependent thermal conductivity on the thermal resistance of GaN/substrate stacks. A combination of parameters such as substrates {diamond, silicon carbide, silicon, and sapphire}, thermal boundary resistance {10–60 m2K/GW}, heat source lengths {10 nm–20 μm}, and power dissipation levels {1–8 W} are studied by using technology computer-aided design (TCAD) software Synopsys. Among diamond, silicon carbide, silicon, and sapphire substrates, the diamond provides the lowest thermal resistance due to its superior thermal conductivity. We report that due to non-zero thermal boundary resistance and localized heating in GaN-based high electron mobility transistors, an optimum separation between the heat source and substrate exists. For high power (i.e., 8 W) heat dissipation on high thermal conductive substrates (i.e., diamond), the optimum separation between the heat source and substrate becomes submicron thick (i.e., 500 nm), which reduces the hotspot temperature as much as 50 °C compared to conventional multi-micron thick case (i.e., 4 μm). This is attributed to the thermal conductivity drop in GaN near the heat source. Improving the TBR between GaN and diamond increases temperature reduction by our further approach. Overall, we provide thermal management design guidelines for GaN-based devices.