Estimation of statistical variation in temporal NBTI degradation and its impact on lifetime circuit performance
- 1 November 2007
- conference paper
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE) in 2006 IEEE/ACM International Conference on Computer Aided Design
- No. 10923152,p. 730-734
- https://doi.org/10.1109/iccad.2007.4397352
Abstract
Negative bias temperature instability (NBTI) in MOSFETs is one of the major reliability concerns in sub-100 nm technologies. So far, studies of NBTI and its impact on circuit performance have assumed an average behavior of the degradation process. However, in very short channel devices, finite number of Si-H bonds in the channel can induce a statistical random variation of the degradation process. This results in significant random Vt variations in PMOS transistor. The NBTI induced variation depends on operating temperature and the effective stress period for the specific device. In this paper, we analyze the impact of stochastic temporal NBTI variations and propose a compact circuit level Vt model. Using the proposed model, we show how temporal Vt variations can affect the lifetime performance of different circuit topologies including 6T SRAM cell and random combinational logic circuits.Keywords
This publication has 13 references indexed in Scilit:
- Characterization and estimation of circuit reliability degradation under NBTI using on-line IDDQmeasurementProceedings of the 39th conference on Design automation - DAC '02, 2007
- Statistical timing analysis using levelized covariance propagation considering systematic and random variations of process parametersACM Transactions on Design Automation of Electronic Systems, 2006
- Impact of NBTI on SRAM Read Stability and Design for ReliabilityPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2006
- Impact of NBTI Induced Statistical Variation to SRAM Cell StabilityPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2006
- Impact of NBTI on the temporal performance degradation of digital circuitsIEEE Electron Device Letters, 2005
- Statistical design and optimization of SRAM cell for yield enhancementPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- A comprehensive framework for predictive modeling of negative bias temperature instabilityPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2004
- A critical examination of the mechanics of dynamic NBTI for PMOSFETsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2004
- The statistics of NBTI-induced V/sub T/ and β mismatch shifts in pMOSFETsIEEE Transactions on Device and Materials Reliability, 2002
- Static-noise margin analysis of MOS SRAM cellsIEEE Journal of Solid-State Circuits, 1987