Impact of NBTI on SRAM Read Stability and Design for Reliability
- 7 April 2006
- conference paper
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE) in 7th International Symposium on Quality Electronic Design (ISQED'06)
- p. 6 pp.-218
- https://doi.org/10.1109/isqed.2006.73
Abstract
Negative bias temperature instability (NBTI) has the potential to become one of the main show-stoppers of circuit reliability in nanometer scale devices due to its deleterious effects on transistor threshold voltage. The degradation of PMOS devices due to NBTI leads to reduced temporal performance in digital circuits. We have analyzed the impact of NBTI on the read stability of SRAM cells. The amount of degradation in static noise margin (SNM) which is a measure of the read stability of the 6-T SRAM cell has been estimated using reaction-diffusion (R-D) model. We propose a simple solution to recover the SNM of the SRAM cell using a data flipping technique and present the results simulated on BPTM 70nm and 100nm technology. We also compare and evaluate different implementation methodologies for the proposed techniqueKeywords
This publication has 21 references indexed in Scilit:
- Mechanism of dynamic NBTI of pMOSFETsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- Oxide field dependence of interface trap generation during negative bias temperature instability in PMOSPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- A critical examination of the mechanics of dynamic NBTI for PMOSFETsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2004
- Universal recovery behavior of negative bias temperature instability [PMOSFETs]Published by Institute of Electrical and Electronics Engineers (IEEE) ,2004
- Mechanism of negative bias temperature instability in CMOS devices degradation, recovery and impact of nitrogenPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2004
- Transient effects and characterization methodology of negative bias temperature instability in pMOS transistorsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Time and voltage dependence of degradation and recovery under pulsed negative bias temperature stressPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Negative bias temperature instability of deep sub-micron p-MOSFETs under pulsed bias stressPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Mechanism and process dependence of negative bias temperature instability (NBTI) for pMOSFETs with ultrathin gate dielectricsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Negative bias temperature instability (NBTI) in deep sub-micron p/sup +/-gate pMOSFETsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002