High-Performance Deep Submicron Ge pMOSFETs With Halo Implants
- 27 August 2007
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 54 (9), 2503-2511
- https://doi.org/10.1109/ted.2007.902732
Abstract
Ge pMOSFETs with HfO2 gate dielectric and gate lengths down to 125 nm are fabricated in a Si-like process. Long-channel hole mobilities exceed the universal curve for Si by more than 2.5 times for vertical effective fields as large as 1 MV/cm. The mobility enhancement is found to be relevant at submicron gate lengths, and a drive current of 1034 muA/mum is achieved for L=125 nm at VG-VT=VD=-1.5 V. The introduction of halo implants allows significantly improved control of short-channel effects, with approximately three orders of magnitude reduction in source junction off-current. VT rolloff and drain-induced barrier lowering are reduced from 207 mV and 230 mV/V to 36 mV and 54 mV/V, respectively, for the highest n-well dose investigated. Four key logic benchmarking metrics are used to demonstrate that Ge is able to outperform Si down to the shortest investigated gate length, with an almost twofold improvement in intrinsic gate delay. ION=722 muA/mum is demonstrated for IOFF=11 nA/mum at a power supply voltage of -1.5 V, when evaluating from the source.Keywords
This publication has 14 references indexed in Scilit:
- Electrical characteristics of 8-/spl Aring/ EOT HfO/sub 2//TaN low thermal-budget n-channel FETs with solid-phase epitaxially regrown junctionsIEEE Transactions on Electron Devices, 2006
- High-mobility low band-to-band-tunneling strained-Germanium double-gate heterostructure FETs: SimulationsIEEE Transactions on Electron Devices, 2006
- Demonstration of recessed SiGe S/D and inserted metal gate on HfO/sub 2/ for high performance pFETs.Published by Institute of Electrical and Electronics Engineers (IEEE) ,2006
- Ge Deep Sub-Micron HiK/MG pFET with Superior Drive Compared to Si HiK/MG State-of-the-Art ReferencePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2006
- Manufacturability of 20-nm Ultrathin Body Fully Depleted SOI Devices With FUSI Metal GatesIEEE Transactions on Semiconductor Manufacturing, 2005
- Epitaxial strained germanium p-MOSFETs with HfO/sub 2/ gate dielectric and TaN gate electrodePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2004
- Ultrahigh room-temperature hole Hall and effective mobility in Si0.3Ge0.7/Ge/Si0.3Ge0.7 heterostructuresApplied Physics Letters, 2002
- CMOS scaling into the 21st century: 0.1 µm and beyondIBM Journal of Research and Development, 1995
- On the universality of inversion layer mobility in Si MOSFET's: Part I-effects of substrate impurity concentrationIEEE Transactions on Electron Devices, 1994
- The Transistor, A Semi-Conductor TriodePhysical Review B, 1948