Field Enhancement for Dielectric Layer of High-Voltage Devices on Silicon on Insulator

Abstract

Based on the continuity theorem of electric displacement including interface charges, the enhanced dielectric layer field (ENDIF) for silicon-on-insulator (SOI) high-voltage devices is proposed. The following three approaches for enhancing the dielectric layer electric field E_I to increase the vertical breakdown voltage of a device V_B,V are presented: 1) using a thin silicon layer with a high critical electric field E_S,C ; 2) introducing a low-permittivity dielectric buried layer; and 3) implementing interface charges between the silicon and the dielectric layer. Considering the threshold energy of silicon epsiv_T, the formula of E_S,C on silicon layer thickness t_S is first obtained, which increases sharply with a decrease of t_S, and reaches up to 141 V/mum at t_S = 0.1 mum. Expressions for E_I and VByV are given, which agree well with simulative and experimental results. Based on the ENDIF, the new device structures are given, and an E_I value of 300 V/mum has been experimentally obtained for double-sided trench SOI. Moreover, several conventional SOI devices are explained well by ENDIF.