Compile-time decided instruction cache locking using worst-case execution paths
- 30 September 2007
- conference paper
- conference paper
- Published by Association for Computing Machinery (ACM)
- p. 143-148
- https://doi.org/10.1145/1289816.1289853
Abstract
No abstract availableKeywords
This publication has 4 references indexed in Scilit:
- Cache Contents Selection for Statically-Locked Instruction Caches: An Algorithm ComparisonPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2006
- WCET-Centric Software-controlled Instruction Caches for Hard Real-Time SystemsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2006
- Influence of Memory Hierarchies on Predictability for Time Constrained Embedded SoftwarePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- Data cache locking for higher program predictabilityPublished by Association for Computing Machinery (ACM) ,2003